Fast Hardware Algorithm for Division in hbox 2m Based on the Extended Euclid's Algorithm With Parallelization of Modular Reductions

We propose a fast hardware algorithm for division in GF(2) based on the extended Euclid’s algorithm. The algorithm requires only one iteration to perform the operations that correspond to the ones performed in two iterations of previously reported division algorithms. Since the algorithm performs modular reductions in parallel by changing the order of execution of the operations, a circuit based on this algorithm has almost the same critical path delay as the previously proposed ones. The circuit computes division in m clock cycles, whereas the previously proposed circuits take 2m − 1 or more clock cycles.